In EEPROM memories, the logical value of a bit is stored in a memory cell usually comprising an access transistor and a state transistor having a control gate and a floating gate.
The programming or the erasing of a floating-gate transistor consists in the injection or the extraction of electrical charges into or from the gate of the transistor by tunnel effect (“Fowler-Nordheim effect”) by means of a high voltage pulse Vp which can be of the order of 10 to 20 volts, typically 13 volts.
This high voltage of 13 volts, necessary for writing EEPROM memories, cannot be reduced and imposes tight constraints with regard to the technological processes and the reliability of the product.
Indeed, lithographic reduction, in other words increasing the etch resolution, leads to a decrease in the operating voltages, and this high write voltage becomes more problematic notably with regard to breakdowns or leakages from the source/drain junctions of the transistors to the substrate generally connected to ground.
These risks of leakages and of premature aging of the transistors have a direct impact on the reliability of the product and the maximum high voltage Vp applicable is limited by the robustness of the memory cells.
As a consequence, the voltage Vp may be insufficient for the erase and programming operations to take place correctly or the memory cells may even be degraded.
Furthermore, when the voltage Vp comes close to the maximum voltages permitted for the components in question, large leakage currents appear, generally by the avalanche effect. These currents increase significantly above a certain threshold and a charge pump can no longer supply them. This may lead to an under-erasing or an under-programming, and these leakage risks thus have a direct impact on the functionality of the circuit
Maximizing the coupling factor of the memory cells and minimizing the thickness of the tunnel oxide have allowed this problem to be addressed, but these techniques have reached their maximum possibilities (coupling factor exceeding 80% and thickness of tunnel oxide less than 70 Å).
An increase in the duration of application of the erase and programming high-voltage pulses is limited since this could lead to unacceptable write times.
Alternative solutions, such as for example an architecture known as a “split-voltage” architecture (according to terminology generally used by those skilled in the art) have been envisaged, but generally require complex peripheral circuits and are poorly adapted notably to small memory planes, consuming very little power, for example used in radio frequency identification (“RFID”) tags or autonomous memories.